1. Field of the Invention
The present invention generally relates to circuit design methodologies and, more particularly, to improved buffer tree logic design and optimization.
2. Description of the Related Art
A prevalent method of digital logic design is the Application Specific Integrated Circuit (ASIC) design method. The ASIC design approach abstracts individual transistor configurations that perform certain logic functions (such as a two input “nand”) into what is referred to as a “standard cell.” A library of standard cells is typically created and provided by an ASIC library vendor, with predetermined characteristics for each of the ASIC cells. Besides functional characteristics, cells are made available with different physical traits such as input pin capacitance or output drive strength. An integrated circuit chip is created by interconnecting these cells by wires into a network, assigning locations for those cells on the chip and assigning specific routes to the wires. This network is represented as a netlist.
Typically, these standard cell implementations can be used by the logic designer with a set of automated design tools that perform a variety of tasks to implement an ASIC design. One such design automation task, commonly referred to as “physical synthesis” involves “placed” ASIC circuit components, where a “placement tool” has assigned real or approximate physical locations for individual cells, designating where those cells should be realized on the physical chip. The choice of what ASIC cells are used from the target ASIC library to implement the logic function has been typically made by a preceding tool referred to as “logic synthesis”. Wires (conductive lines) interconnecting those cells to form a desired logic function may be logically present but may not have been assigned a physical topology at the time physical synthesis is performed. The physical synthesis tool, dealing with these “placed” ASIC circuit components, optimizes the circuit choices (e.g., selecting specific cells from the library) and their physical locations to satisfy various design criteria (e.g., particular timing, power dissipation, etc.). These optimizations are made while satisfying other requirements, such as physical constraints that no two ASIC cells can occupy the same location. This is the a basic minimum definition of a Physical synthesis tool; modern physical synthesis tools have come to include other design processes such as logic synthesis and placement.
One important optimization made by a physical synthesis tool is the addition of buffering logic to maintain the integrity of a digital signal being sent from one ASIC cell to another across a wire. As an electrical signal travels along a physical wire, the shape of the signal can become attenuated over distance such that it is difficult (since the transition from one logic value to another takes longer) or even impossible for a receiving ASIC cell to detect a logic change in a signal that is propagated too far. In an effort to reduce attenuation and achieve optimal time of flight for a logic signal, buffering ASIC cells are typically inserted on many nets (signal paths) in the design. This distribution of a logic value from one location in the design to others is generally referred to as “buffering” and is inclusive of distribution of the logic value and the complement of that value. The network of buffering and inverting cells are together referred to as a buffer tree or buffering network. Considering both true and complement distribution simultaneously is typically needed to attain the best resultant tree.
The performance of an ASIC circuit is often modeled by a static timing tool that reports what is the worst possible timing event that could take place across the circuit between elements. The quality of timing at any point in the design is usually expressed by the “slack” at that point, which is calculated as the time the signal needs to be at that point minus when it actually arrives at that point. A negative slack indicates a signal arrives at some location after it is needed. The buffering sub-system of ASIC design tools attempts to remove any points with negative slack by the strategic placement of buffers.
Optimizing a buffer tree's design (insertion and placement) is critical as the operating speed of ASIC designs continues to increase. Strategic placement of buffers can significantly reduce propagation delays caused by excessive wire length. This placement can be guided by simulations involving computations of signal propagation delay between cells. Accurate computations of propagation delay within a signal path, which are utilized in optimization algorithms to determine buffer locations, typically involve complex equations and can be time consuming. As ASIC designs often have several million placeable ASIC cells, as well as several million interconnecting wires, optimizing every signal path for an entire circuit can be very time consuming, taking days or even weeks. In some cases, various buffer optimizations may be made at various stages of the design (e.g., during logical modeling at the cell level), while the number of buffer trees is more manageable than in the finished design. However, such optimizations may prove sub-optimal when cells are combined to produce the finished product, or a larger tree.
Accordingly, what is needed is an improved technique for optimizing buffer trees within an integrated circuit that is computationally efficient.